Freescale Semiconductor /MK60DZ10 /UART5 /C4

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Interpret as C4

7 43 0 0 00 0 0 0 0 0 0 0 0BRFA0 (0)M10 0 (0)MAEN2 0 (0)MAEN1

M10=0, MAEN1=0, MAEN2=0

Description

UART Control Register 4

Fields

BRFA

Baud Rate Fine Adjust

M10

10-bit Mode select

0 (0): The parity bit is the ninth bit in the serial transmission.

1 (1): The parity bit is the tenth bit in the serial transmission.

MAEN2

Match Address Mode Enable 2

0 (0): All data received is transferred to the data buffer if MAEN1 is cleared.

1 (1): All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.This bit must be cleared when C7816[ISO7816E] is set/enabled.

MAEN1

Match Address Mode Enable 1

0 (0): All data received is transferred to the data buffer if MAEN2 is cleared.

1 (1): All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.This bit must be cleared when C7816[ISO7816E] is set/enabled.

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